Hardware/NAND Interface: Difference between revisions
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== Register Details == | == Register Details == | ||
{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = | {{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 5 | | ||
|1|1|1|1|1|1|1|1|8| | |1|1|1|1|1|1|1|1|8| | ||
|R/W|W|U|W|W|W|W|W|W| | |R/W|W|U|W|W|W|W|W|W| | ||
|EXEC|IRQ||A5|A4|A3|A2|A1|COMMAND|| | |EXEC|IRQ||A5|A4|A3|A2|A1|COMMAND|| | ||
| | |1|1|1|1|12| | ||
|W|W| | |W|W|W|W|W| | ||
| | |WAIT|WR|RD|ECC|DMALEN| | ||
}} | }} | ||
This register controls the state of the NAND interface. | This register controls the state of the NAND interface. | ||
| Line 34: | Line 34: | ||
|A1|Send first address byte (typ. column address low) | |A1|Send first address byte (typ. column address low) | ||
|COMMAND|8-bit NAND command | |COMMAND|8-bit NAND command | ||
| | |WAIT|Wait for R/B to go high between address and data phases (wait for read/write/erase){{check}} | ||
|DMALEN|Number of bytes to | |WR|Transfer data to the NAND chip{{check}} | ||
|RD|Transfer data from the NAND chip{{check}} | |||
|ECC|Calculate ECC or transfer ECC data or ?? {{check}} | |||
|DMALEN|Number of bytes to transfer | |||
}} | }} | ||
---- | ---- | ||
Revision as of 22:03, 27 February 2009
| NAND Interface | |
| Access | |
|---|---|
| Broadway | None |
| Starlet | Full |
| Registers | |
| Base | 0x0d010000 |
| Length | 0x20 |
| Access size | 32 bits |
| Byte order | Big Endian |
Register List
| NAND Interface | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d010000 | 32 | NAND_CTRL | NAND Control and Status |
| 0x0d010004 | 32 | NAND_CONFIG | ?? |
| 0x0d010008 | 32 | NAND_ADDR1 | Address bytes 1-2 (column) |
| 0x0d01000c | 32 | NAND_ADDR2 | Address bytes 3-5 (row) |
| 0x0d010010 | 32 | NAND_DATABUF | Memory address of the Data buffer |
| 0x0d010014 | 32 | NAND_ECCBUF | Memory address of the Spare buffer |
Register Details
| NAND_CTRL (0x0d010000) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | W | U | W | W | W | W | W | W | |||||||
| Field | EXEC | IRQ | A5 | A4 | A3 | A2 | A1 | COMMAND | ||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | W | W | W | W | W | |||||||||||
| Field | WAIT | WR | RD | ECC | DMALEN | |||||||||||
This register controls the state of the NAND interface.
| Field | Description |
| EXEC | Write 1: initiate NAND command Read: NAND interface busy |
| IRQ | Set to enable IRQ generation when command is complete |
| A5 | Send fifth address byte (typ. row address high) |
| A4 | Send fourth address byte (typ. row address mid) |
| A3 | Send third address byte (typ. row address low) |
| A2 | Send second address byte (typ. column address high) |
| A1 | Send first address byte (typ. column address low) |
| COMMAND | 8-bit NAND command |
| WAIT | Wait for R/B to go high between address and data phases (wait for read/write/erase)[check] |
| WR | Transfer data to the NAND chip[check] |
| RD | Transfer data from the NAND chip[check] |
| ECC | Calculate ECC or transfer ECC data or ?? [check] |
| DMALEN | Number of bytes to transfer |
| NAND_CONF (0x0d010004) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | ? | |||||||||||||||
| Field | Unknown | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | ? | |||||||||||||||
| Field | Unknown | |||||||||||||||
This register probably configures certain aspects of the NAND interface (timings?)[check]. The bit definitions are unknown. This register is written with the values 0x08000000 and 0x4b3e0e7f during initialization.
| NAND_ADDR1 (0x0d010008) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | U | |||||||||||||||
| Field | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | R/W | ||||||||||||||
| Field | ADDR2 | ADDR1 | ||||||||||||||
This register contains the first two address bytes that can be sent to the NAND chip. Normally it contains the column address (offset within a page).
| Field | Description |
| ADDR2 | Second address byte |
| ADDR1 | First address byte |
| NAND_ADDR2 (0x0d01000c) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | U | R/W | ||||||||||||||
| Field | ADDR5 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | R/W | ||||||||||||||
| Field | ADDR4 | ADDR3 | ||||||||||||||
This register contains the last three address bytes that can be sent to the NAND chip. Normally it contains the row address (page number).
| Field | Description |
| ADDR5 | Fifth address byte |
| ADDR4 | Fourth address byte |
| ADDR3 | Third address byte |
| NAND_DATABUF (0x0d010010) | |
| 310 | |
| Access | R/W |
This register contains the DMA address of the page data buffer (0x800 bytes)
| NAND_ECCBUF (0x0d010014) | |
| 310 | |
| Access | R/W |
This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome).