Hardware/AES engine: Difference between revisions
No edit summary |
No edit summary |
||
Line 6: | Line 6: | ||
| hwdirq = 2 | | hwdirq = 2 | ||
}} | }} | ||
The Hollywood's AES Engine encrypts/decrypts 16-byte blocks using AES-128 in Cipher Block Chaining mode. | |||
== Register List == | |||
{{reglist|NAND Interface}} | |||
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}} | |||
| | {{rla|0x0d020004|32|AES_SRC|Source memory address}} | ||
|| | {{rla|0x0d020008|32|AES_DEST|Destination memory address}} | ||
| | {{rla|0x0d02000c|32|AES_KEY|Key FIFO}} | ||
{{rla|0x0d020010|32|AES_IV|IV FIFO}} | |||
| | |||
|| | |||
| | |||
|} | |} | ||
== Register Details == | |||
{{reg32 | AES_CTRL | addr = 0x0d020000 | hifields = 6 | lofields = 4 | | |||
|1|1|1|1|1|7| | |||
|R/W|R/W|R?|R/W|R/W|U| | |||
|EXEC|IRQ|ERR|CMD|MODE||| | |||
|3|1|12| | |||
|U|W|W| | |||
||IV||BLOCKS| | |||
}} | |||
This register controls the state of the AES engine. | |||
{{regdesc | |||
|EXEC|Write 1: initiate AES command<br/>Read: AES engine busy | |||
|IRQ|Set to enable IRQ generation when command is complete | |||
|ERR|If set, AES error occured (?){{check}} | |||
|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?). | |||
|MODE|0 for encrypt, 1 for decrypt. | |||
|IV|If set, use the supplied IV. If clear, chain from last command (continue CBC mode). | |||
|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block. | |||
}} | |||
---- | |||
{{regsimple | AES_SRC | addr = 0x0d020004 | bits = 32 | access = R/W }} | |||
This register contains the DMA address of the source data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned). | |||
---- | |||
{{regsimple | AES_SRC | addr = 0x0d020008 | bits = 32 | access = R/W }} | |||
This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned). | |||
---- | |||
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }} | |||
This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word). | |||
---- | |||
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }} | |||
This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word). | |||
Set the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block. |
Revision as of 21:03, 10 March 2009
AES engine | |
Access | |
---|---|
Broadway | None |
Starlet | Full |
Registers | |
Base | 0x0d020000 |
Length | 0x14 |
Access size | 32 bits |
Byte order | Big Endian |
IRQs | |
Hollywood | 2 |
The Hollywood's AES Engine encrypts/decrypts 16-byte blocks using AES-128 in Cipher Block Chaining mode.
Register List
NAND Interface | |||
---|---|---|---|
Address | Bits | Name | Description |
0x0d020000 | 32 | AES_CTRL | AES Control and Status |
0x0d020004 | 32 | AES_SRC | Source memory address |
0x0d020008 | 32 | AES_DEST | Destination memory address |
0x0d02000c | 32 | AES_KEY | Key FIFO |
0x0d020010 | 32 | AES_IV | IV FIFO |
Register Details
AES_CTRL (0x0d020000) | |||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ||
Access | R/W | R/W | R? | R/W | R/W | U | |||||||||||
Field | EXEC | IRQ | ERR | CMD | MODE | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
Access | W | W | colspan="
" | | ||||||||||||||
Field | BLOCKS | colspan="
" | B12 |
This register controls the state of the AES engine.
Field | Description |
EXEC | Write 1: initiate AES command Read: AES engine busy |
IRQ | Set to enable IRQ generation when command is complete |
ERR | If set, AES error occured (?)[check] |
ENA | Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?). |
MODE | 0 for encrypt, 1 for decrypt. |
IV | If set, use the supplied IV. If clear, chain from last command (continue CBC mode). |
DATALEN | Number of 16-byte blocks to process, minus one. 0 means one block. |
AES_SRC (0x0d020004) | |
310 | |
Access | R/W |
This register contains the DMA address of the source data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned).
AES_SRC (0x0d020008) | |
310 | |
Access | R/W |
This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned).
AES_KEY (0x0d02000c) | |
310 | |
Access | W |
This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).
AES_KEY (0x0d02000c) | |
310 | |
Access | W |
This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word). Set the IV bit in the AES_CTRL register to restart the CBC encryption using this IV instead of using the last encrypted block.