Hardware/NAND Interface

NAND Interface
Access
Broadway	None
Starlet	Full
Registers
Base	0x0d010000
Length	0x20
Access size	32 bits
Byte order	Big Endian

NAND Interface
Address	Bits	Name	Description
0x0d010000	32	NAND_CTRL
0x0d010004	32	NAND_CONFIG
0x0d010008	32	NAND_ADDR1
0x0d01000C	32	NAND_ADDR2
0x0d010010	32	NAND_DATABUF
0x0d010014	32	NAND_ECCBUF

NAND_CTRL (0x0d010000)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	R/W	W	U	W					W
Field	EXEC	IRQ		ADDR_MASK					COMMAND
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	W				W
Field	FLAGS				DMALEN

This register controls the state of the NAND interface.

Field	Description
EXEC	Write 1: initiate NAND command Read: NAND interface busy
IRQ	Set to enable IRQ generation
ADDR_MASK	Mask of the address bytes to send (10 = AA, 08 = BB, ..., 01 = FF)
COMMAND	8-bit NAND command
FLAGS	TBD
DMALEN	Number of bytes to copy

base	function	offset	description	contents/example
0x0D010000	NAND
		0000 W	command	9F000000 (CMD 00: start read sector)
				8030B840 (CMD 30: data (starts DMA 0x840 bytes))
				80FF8000 (CMD FF: reset)
				00008000 means: wait for R/#B to go down
				1F000000 is the mask of the address bytes to send. (10 = AA, 08 = BB, .., 01 = FF in 08,0c)
		0000 R	status	MSB means busy
		0004 W	config
		0008 W	address #0	0000AABB
		000C W	address #1	CCDDEEFF, NAND sector, multiply with 0x800 or 0x840 to get offset, 0x40 for ecc
		0010 W	data addr	target address for DMA (0x800 main bytes)
		0014 W	ecc addr	target address for DMA (0x40 spare bytes + 0x10 byte HW-calculated ECC syndrome)
		0018 W	unknown