Difference between revisions of "Hardware/Processor Interface"

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m (see last edit)
(Added FIFO Write Pointer)
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| 15-31 || Unused/reserved
 
| 15-31 || Unused/reserved
 
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|}
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{{regsimple | PI_FIFO_WP      | addr=0xCC003014 | bits=32 | access = R/W}}

Revision as of 00:36, 12 July 2010

Processor Interface
Access
BroadwayFull
StarletNone
Registers
Base0x0c003000
Length0x100
Access size32 bits
Byte orderBig Endian
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Interrupt Cause (0x0C003000)

IRQ Description
0 GP Runtime Error
1 Reset Switch
2 DVD
3 Serial
4 EXI
5 AI (Audio Interface)
6 DSP
7 MEM (Memory Interface)
8 VI (Video Interface)
9 PE Token
10 PE Finish
11 CP (Command Processor) FIFO
12 Debugger
13 Highspeed Port
14 Hollywood IRQs
15 Unused/reserved
16 Reset Switch State
17-31 Unused/reserved

Interrupt Mask (0x0C003004)

IRQ Description
0 GP Runtime Error
1 Reset Switch
2 DVD
3 Serial
4 EXI
5 AI (Audio Interface)
6 DSP
7 MEM (Memory Interface)
8 VI (Video Interface)
9 PE Token
10 PE Finish
11 CP (Command Processor) FIFO
12 Debugger
13 Highspeed Port
14 Hollywood IRQs
15-31 Unused/reserved

PI_FIFO_WP (0xCC003014)
  310
Access R/W