Hardware/IPC
| IPC | |
| Hollywood Registers | |
| Access | |
|---|---|
| Broadway | Partial |
| Starlet | Full |
| Registers | |
| Base | 0x0d800000 |
| Length | 0x10 |
| Access size | 32 bits |
| Byte order | Big Endian |
| IRQs | |
| Hollywood | 30, 31 |
The Hollywood's IPC engine is generally used as a signalling system for communications between Starlet and Hollywood. The hardware consists of two general-purpose registers, and two flag pairs. Each side can set either of two flags, and the other side can read them or clear them and configure them to generate a Hollywood interrupt. The hardware is symmetric.
Operation
Conceptually, the IPC system can be seen as four bit flags which may be set or cleared: X1, X2, Y1, and Y2. These same four flags are visible in both control registers in different places. X1 and X2 can be read/set/cleared by the Broadway, but can only be read/cleared by the Starlet. The Starlet can configure individually whether X1 or X2 generate an interrupt (#31). The opposite is true for Y1 and Y2: they can be read/set/cleared by the Starlet, but only read/cleared by the Broadway. The Broadway can configure whether these generate an interrupt (#30).
Note that, since the interrupts can actually route to either or both the Starlet and Broadway, and since the Starlet can also access the Broadway's registers, there are ways of abusing these flags for odd purposes.
Register HW_IPC_ARMCTRL can only be accessed by the Starlet. The other three registers can be accessed by both CPUs.
IOS flag protocol
| Field | Description |
| X1 | Execute command: a new pointer is available in HW_IPC_PPCCTRL |
| Y2 | Command acknowledge |
| Y1 | Command executed and reply available in HW_IPC_ARMMSG |
| X2 | Relaunch |
Register List
| IPC | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800000 | 32 | HW_IPC_PPCMSG | General purpose register 1, conventionally set by the Hollywood |
| 0x0d800004 | 32 | HW_IPC_PPCCTRL | Hollywood flags and control |
| 0x0d800008 | 32 | HW_IPC_ARMMSG | General purpose register 2, conventionally set by the Starlet |
| 0x0d80000c | 32 | HW_IPC_ARMCTRL | Starlet flags and control |
Register Details
| HW_IPC_PPCMSG (0x0d800000) | |
| 310 | |
| Access | R/W |
This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Broadway and read by the Starlet, though this is not a requirement. In IOS, this register contains a pointer to a 0x40-byte structure in memory, documented more in IOS.
| HW_IPC_PPCCTRL (0x0d800004) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | U | |||||||||||||||
| Field | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | R/W | R/Z | R/Z | R/W | |||||||||
| Field | IY2 | IY1 | X2 | Y1 | Y2 | X1 | ||||||||||
| Field | Description |
| X1 | Read/write flag X1 |
| Y2 | Read flag Y2. To clear the flag, write 1 to this bit. |
| Y1 | Read flag Y1. To clear the flag, write 1 to this bit. |
| X2 | Read/write flag X2 |
| IY1 | If set, flag Y1 generates Hollywood interrupt #30 |
| IY2 | If set, flag Y2 generates Hollywood interrupt #30 |
This register exposes the Broadway side of the IPC control. Flags X1 and X2 may be freely set/cleared. Flags Y1 and Y2 can be read and cleared (by writing one), and can optionally generate IRQ #30.
| HW_IPC_ARMMSG (0x0d800008) | |
| 310 | |
| Access | R/W |
This is a general purpose 32-bit register that can be freely read/written by both CPUs. It is usually set by the Starlet and read by the Broadway, though this is not a requirement.
| HW_IPC_ARMCTRL (0x0d80000c) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | U | |||||||||||||||
| Field | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | R/W | R/Z | R/Z | R/W | |||||||||
| Field | IX2 | IX1 | Y2 | X1 | X2 | Y1 | ||||||||||
| Field | Description |
| Y1 | Read/write flag Y1 |
| X2 | Read flag X2. To clear the flag, write 1 to this bit. |
| X1 | Read flag X1. To clear the flag, write 1 to this bit. |
| Y2 | Read/write flag Y2 |
| IX1 | If set, flag X1 generates Hollywood interrupt #31 |
| IX2 | If set, flag X2 generates Hollywood interrupt #31 |
This register exposes the Starlet side of the IPC control. Flags Y1 and Y2 may be freely set/cleared. Flags X1 and X2 can be read and cleared (by writing one), and can optionally generate IRQ #31. The Broadway does not have any kind of access to this register.