| Processor Interface |
| Access |
|---|
| Broadway | Full |
|---|
| Starlet | None |
|---|
| Registers |
|---|
| Base | 0x0c003000 |
|---|
| Length | 0x100 |
|---|
| Access size | 32 bits |
|---|
| Byte order | Big Endian |
|---|
|
Interrupt Cause (0x0C003000)
| IRQ
|
Description
|
| 0 |
GP Runtime Error
|
| 1 |
Reset Switch
|
| 2 |
DVD
|
| 3 |
Serial
|
| 4 |
EXI
|
| 5 |
AI (Audio Interface)
|
| 6 |
DSP
|
| 7 |
MEM (Memory Interface)
|
| 8 |
VI (Video Interface)
|
| 9 |
PE Token
|
| 10 |
PE Finish
|
| 11 |
CP (Command Processor) FIFO
|
| 12 |
Debugger
|
| 13 |
Highspeed Port
|
| 14 |
Hollywood IRQs
|
| 15 |
Unused/reserved
|
| 16 |
Reset Switch State
|
| 17-31 |
Unused/reserved
|
Interrupt Mask (0x0C003004)
| IRQ
|
Description
|
| 0 |
GP Runtime Error
|
| 1 |
Reset Switch
|
| 2 |
DVD
|
| 3 |
Serial
|
| 4 |
EXI
|
| 5 |
AI (Audio Interface)
|
| 6 |
DSP
|
| 7 |
MEM (Memory Interface)
|
| 8 |
VI (Video Interface)
|
| 9 |
PE Token
|
| 10 |
PE Finish
|
| 11 |
CP (Command Processor) FIFO
|
| 12 |
Debugger
|
| 13 |
Highspeed Port
|
| 14 |
Hollywood IRQs
|
| 15-31 |
Unused/reserved
|
| PI_FIFO_WP (0x0C003014)
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
U
|
R
|
R/W
|
| Field
|
|
WRAPPED
|
ADDR
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
R/W
|
U
|
| Field
|
ADDR
|
|
This register holds the current address and state of the CPU FIFO write pointer.
| Field
|
Description
|
| WRAPPED
|
Indicates the write pointer reached the end of the FIFO and wrapped to the start. Note that it is in a different location from the gamecube to allow for MEM2 addresses.
|
| ADDR
|
Word address that will be written to next.
|