From WiiBrew
| Memory Interface |
| Access |
|---|
| Broadway | Full |
|---|
| Starlet | None |
|---|
| Registers |
|---|
| Base | 0x0c004000 |
|---|
| Length | 0x80 |
|---|
| Access size | 16/32 bits |
|---|
| Byte order | Big Endian |
|---|
| IRQs |
|---|
| Broadway | 7 |
|---|
|
Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3. Page addresses are calculated with (physical_address >> 10)
Registers
| MI_PROT_RGN0 (0x0C004000)
|
|
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
|
| Access
| R/W
|
| Field
| First protected page address
|
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
| Access
| R/W
|
| Field
| Last protected page address
|
| MI_PROT_RGN1 (0x0C004004)
|
|
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
|
| Access
| R/W
|
| Field
| First protected page address
|
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
| Access
| R/W
|
| Field
| Last protected page address
|
| MI_PROT_RGN2 (0x0C004008)
|
|
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
|
| Access
| R/W
|
| Field
| First protected page address
|
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
| Access
| R/W
|
| Field
| Last protected page address
|
| MI_PROT_RGN3 (0x0C00400C)
|
|
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
|
| Access
| R/W
|
| Field
| First protected page address
|
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
|
| Access
| R/W
|
| Field
| Last protected page address
|
| MI_PROT_TYPE (0x0C004010)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| U
| R/W
| R/W
| R/W
| R/W
|
| Field
|
| Ch3
| Ch2
| Ch1
| Ch0
|
| Field
| Description
|
| ChX
| 00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
|
| MI_IRQMASK (0x0C00401C)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| U
| ?/W
| ?/W
| ?/W
| ?/W
| ?/W
|
| Field
|
| ChAll
| Ch3
| Ch2
| Ch1
| Ch0
|
| Field
| Description
|
| ChX
| When set, interrupt from that channel is enabled.
|
| ChAll
| When set, all MI interrupts are enabled.
|
| MI_IRQFLAG (0x0C00401E)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| U
| R/W
| R/W
| R/W
| R/W
| R/W
|
| Field
|
| ChAll
| Ch3
| Ch2
| Ch1
| Ch0
|
| Field
| Description
|
| ChX
| When set, IRQ has been requested. Writing 1 clears it.
|
| ChAll
| All MI interrupts. (?)
|
| MI_UNKNOWN1 (0x0C004020)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| U
| ?
| U
|
| Field
|
| Unk
|
|
| Field
| Description
|
| Unk
| ? Set when MI interrupt has been asserted ? Should be cleared by interrupt handler
|
| MI_PROT_ADDRLO (0x0C004022)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| R/?
| U
|
| Field
| Low
|
|
| MI_PROT_ADDRHI (0x0C004024)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| U
| R/?
|
| Field
|
| High
|
| Field
| Description
|
| High
| Bits 29->16 of the address that the protection exception occurred on.
|
| Low
| Bits 15->5 of the address that the protection exception occurred on.
|
| MI_TIMER0H (0x0C004032)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER0L (0x0C004034)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER1H (0x0C004036)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER1L (0x0C004038)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER2H (0x0C00403A)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER2L (0x0C00403C)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER3H (0x0C00403E)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER3L (0x0C004040)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER4H (0x0C004042)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER4L (0x0C004044)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER5H (0x0C004046)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER5L (0x0C004048)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER6H (0x0C00404A)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER6L (0x0C00404C)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER7H (0x0C00404E)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER7L (0x0C004050)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER8H (0x0C004052)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER8L (0x0C004054)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER9H (0x0C004056)
|
|
| 150
|
| Access
| R/?
|
| MI_TIMER9L (0x0C004058)
|
|
| 150
|
| Access
| R/?
|
| Field
| Description
|
| Timer
| Writing anything to a timer resets it to 0.
|
| MI_UNKNOWN2 (0x0C00405A)
|
|
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|
| Access
| U
| R/?
|
| Field
| ?
| Unk
|
| Field
| Description
|
| Unk
| Possibly something timer related?
|
