| Memory Interface |
| Access |
|---|
| Broadway | Full |
|---|
| Starlet | Full |
|---|
| Registers |
|---|
| Base | 0x0c004000 |
|---|
| Length | 0x80 |
|---|
| Access size | 16 bits |
|---|
| Byte order | Big Endian |
|---|
| IRQs |
|---|
| Broadway | 7 |
|---|
|
This is most likely the same as (or at least mostly similar to) the Memory Interface on the Flipper chip (see YAGCD).
These registers are used by some programs (running on Broadway) to perform indirect accesses on the Memory Controller registers.
The Memory Interface is also exposed to Hollywood starting at 0x0d8b4000.
| Memory Interface Registers
|
| Address
|
Bits
|
Name
|
Description
|
| 0x0d8b4000
|
16
|
MEM_MARR0_START
|
Memory Protection
|
| 0x0d8b4002
|
16
|
MEM_MARR0_END
|
| 0x0d8b4004
|
16
|
MEM_MARR1_START
|
| 0x0d8b4006
|
16
|
MEM_MARR1_END
|
| 0x0d8b4008
|
16
|
MEM_MARR2_START
|
| 0x0d8b400a
|
16
|
MEM_MARR2_END
|
| 0x0d8b400c
|
16
|
MEM_MARR3_START
|
| 0x0d8b400e
|
16
|
MEM_MARR3_END
|
| 0x0d8b4010
|
16
|
MEM_MARR_CONTROL
|
MARR{0-3} permissions
|
| 0x0d8b4012
|
16
|
MEM_CP_BW_DIAL
|
Bandwidth Dial (Command Processor)
|
| 0x0d8b4014
|
16
|
MEM_TC_BW_DIAL
|
Bandwidth Dial (Texture Control)
|
| 0x0d8b4016
|
16
|
MEM_PE_BW_DIAL
|
Bandwidth Dial (Pixel Engine)
|
| 0x0d8b4018
|
16
|
MEM_CPUR_BW_DIAL
|
Bandwidth Dial (CPU read)
|
| 0x0d8b401a
|
16
|
MEM_CPUW_BW_DIAL
|
Bandwidth Dial (CPU write)
|
| 0x0d8b401c
|
16
|
MEM_INT_ENBL
|
MARR interrupt enable
|
| 0x0d8b401e
|
16
|
MEM_INT_STAT
|
MARR interrupt status
|
| 0x0d8b4020
|
16
|
MEM_INT_CLR
|
MARR interrupt clear/mask (?)
|
| 0x0d8b4022
|
16
|
MEM_INT_ADDRL
|
MARR interrupt address (lo bits)
|
| 0x0d8b4024
|
16
|
MEM_INT_ADDRH
|
MARR interrupt address (hi bits)
|
| 0x0d8b4026
|
16
|
MEM_REFRESH
|
| 0x0d8b4028
|
16
|
MEM_CONFIG
|
| 0x0d8b402a
|
16
|
MEM_LATENCY
|
| 0x0d8b402c
|
16
|
MEM_RDTORD
|
| 0x0d8b402e
|
16
|
MEM_RDTOWR
|
| 0x0d8b4030
|
16
|
MEM_WRTORD
|
| 0x0d8b4032
|
16
|
MEM_CP_REQCOUNTH
|
Memory Request Count (Command Processor) (hi bits)
|
| 0x0d8b4034
|
16
|
MEM_CP_REQCOUNTL
|
Memory Request Count (Command Processor) (lo bits)
|
| 0x0d8b4036
|
16
|
MEM_TC_REQCOUNTH
|
Memory Request Count (Texture Control) (hi bits)
|
| 0x0d8b4038
|
16
|
MEM_TC_REQCOUNTL
|
Memory Request Count (Texture Control) (lo bits)
|
| 0x0d8b403a
|
16
|
MEM_CPUR_REQCOUNTH
|
Memory Request Count (CPU read) (hi bits)
|
| 0x0d8b403c
|
16
|
MEM_CPUR_REQCOUNTL
|
Memory Request Count (CPU read) (lo bits)
|
| 0x0d8b403e
|
16
|
MEM_CPUW_REQCOUNTH
|
Memory Request Count (CPU write) (hi bits)
|
| 0x0d8b4040
|
16
|
MEM_CPUW_REQCOUNTL
|
Memory Request Count (CPU write) (lo bits)
|
| 0x0d8b4042
|
16
|
MEM_DSP_REQCOUNTH
|
Memory Request Count (DSP) (hi bits)
|
| 0x0d8b4044
|
16
|
MEM_DSP_REQCOUNTL
|
Memory Request Count (DSP) (lo bits)
|
| 0x0d8b4046
|
16
|
MEM_IO_REQCOUNTH
|
Memory Request Count (I/O) (hi bits)
|
| 0x0d8b4048
|
16
|
MEM_IO_REQCOUNTL
|
Memory Request Count (I/O) (lo bits)
|
| 0x0d8b404a
|
16
|
MEM_VI_REQCOUNTH
|
Memory Request Count (Video Interface) (hi bits)
|
| 0x0d8b404c
|
16
|
MEM_VI_REQCOUNTL
|
Memory Request Count (Video Interface) (lo bits)
|
| 0x0d8b404e
|
16
|
MEM_PE_REQCOUNTH
|
Memory Request Count (Pixel Engine) (hi bits)
|
| 0x0d8b4050
|
16
|
MEM_PE_REQCOUNTL
|
Memory Request Count (Pixel Engine) (lo bits)
|
| 0x0d8b4052
|
16
|
MEM_RF_REQCOUNTH
|
| 0x0d8b4054
|
16
|
MEM_RF_REQCOUNTL
|
| 0x0d8b4056
|
16
|
MEM_FI_REQCOUNTH
|
| 0x0d8b4058
|
16
|
MEM_FI_REQCOUNTL
|
| 0x0d8b405a
|
16
|
MEM_DRV_STRENGTH
|
| 0x0d8b405c
|
16
|
MEM_REFRSH_THHD
|
| 0x0d8b4060
|
16
|
MEM_CPUAHMR_REQCOUNTH
|
| 0x0d8b4062
|
16
|
MEM_CPUAHMR_REQCOUNTL
|
| 0x0d8b4064
|
16
|
MEM_CPUAHMW_REQCOUNTH
|
| 0x0d8b4066
|
16
|
MEM_CPUAHMW_REQCOUNTL
|
| 0x0d8b4068
|
16
|
MEM_DMAAHMR_REQCOUNTH
|
| 0x0d8b406a
|
16
|
MEM_DMAAHMR_REQCOUNTL
|
| 0x0d8b406c
|
16
|
MEM_DMAAHMW_REQCOUNTH
|
| 0x0d8b406e
|
16
|
MEM_DMAAHMW_REQCOUNTL
|
| 0x0d8b4070
|
16
|
MEM_ACC_REQCOUNTH
|
| 0x0d8b4072
|
16
|
MEM_ACC_REQCOUNTL
|
| 0x0d8b4074
|
16
|
MEM_DDRREG_ADDR
|
DDR register offset
|
| 0x0d8b4076
|
16
|
MEM_DDRREG_DATA
|
DDR register data
|
| 0x0d8b4078
|
16
|
MEM_DRV_PSTRENGTH
|
Memory Protection
The MARR registers are used to configure memory protection (where the granularity of particular regions are defined as a chunk of pages).
Protected memory is always 1 page long (where page size is 1024 bytes).
If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised.
Page addresses are calculated with (physical_address >> 10). [check]
| MEM_MARR0_START (0x0C004000)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR0_END (0x0C004002)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR1_START (0x0C004004)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR1_END (0x0C004006)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR2_START (0x0C004008)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR2_END (0x0C00400a)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR3_START (0x0C00400c)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR3_END (0x0C00400e)
|
|
|
150
|
| Access
|
R/W
|
| MEM_MARR_CONTROL (0x0C004010)
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
| Access
|
U
|
R/W
|
R/W
|
R/W
|
R/W
|
| Field
|
|
Ch3
|
Ch2
|
Ch1
|
Ch0
|
| Field
|
Description
|
| ChX
|
00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
|
| MEM_INT_ENBL (0x0C00401C)
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
| Access
|
U
|
?/W
|
?/W
|
?/W
|
?/W
|
?/W
|
| Field
|
|
ChAll
|
Ch3
|
Ch2
|
Ch1
|
Ch0
|
| Field
|
Description
|
| ChX
|
When set, interrupt from that channel is enabled.
|
| ChAll
|
When set, all MI interrupts are enabled.
|
| MEM_INT_STAT (0x0C00401E)
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
| Access
|
U
|
R/W
|
R/W
|
R/W
|
R/W
|
R/W
|
| Field
|
|
ChAll
|
Ch3
|
Ch2
|
Ch1
|
Ch0
|
| Field
|
Description
|
| ChX
|
When set, IRQ has been requested. Writing 1 clears it.
|
| ChAll
|
All MI interrupts. (?)
|
| MEM_INT_CLR (0x0C004020)
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
| Access
|
U
|
?
|
U
|
| Field
|
|
Unk
|
|
| Field
|
Description
|
| Unk
|
? Set when MI interrupt has been asserted ? Should be cleared by interrupt handler
|
| MEM_INT_ADDRL (0x0C004022)
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
| Access
|
R/?
|
U
|
| Field
|
Low
|
|
| MEM_INT_ADDRH (0x0C004024)
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
| Access
|
U
|
R/?
|
| Field
|
|
High
|
| Field
|
Description
|
| High
|
Bits 29->16 of the address that the protection exception occurred on.
|
| Low
|
Bits 15->5 of the address that the protection exception occurred on.
|